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CY28347
Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems
Features
* Supports VIA P4M266/KM266 chipsets * Supports * Provides -- Two different programmable CPU clock pairs -- Six differential DDR SDRAM pairs -- Two low-skew/low-jitter AGP clocks -- Six low-skew/low-jitter PCI clocks -- One 48M output for USB -- One programmable 24M or 48M for SIO * Dial-a-Frequency and Dial-a-dB features * Spread Spectrum for best electromagnetic interference (EMI) reduction * SMBus-compatible for programmability * 56-pin SSOP and TSSOP packages Pentium(R) 4, Athlon processors * Supports two DDR DIMMS Table 1. Frequency Selection Table FS(3:0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 CPU 66.80 100.20 120.00 133.33 72.00 105.00 160.00 140.00 77.00 110.00 180.00 150.00 90.00 100.00 200.00 133.33 AGP 66.80 66.80 60.00 66.67 72.00 70.00 64.00 70.00 77.00 73.33 60.00 60.00 60.00 66.67 66.67 66.67 PCI 33.40 33.40 30.00 33.33 36.00 35.00 32.00 35.00 38.50 36.67 30.00 30.00 30.00 33.33 33.33 33.33
Block Diagram
XIN XOUT VDDR XTAL REF0 VDDI SELP4_K7# VDDC CPUT/CPU0D_T CPUC/CPU0D_C VDDPCI FS3 FS1 PCI(3:5) PCI_F MULTSEL PCI2 PCI1 VDDAGP AGP(0:1) REF(0:1) CPUCS_T CPUCS_C
Pin Configuration[1]
*FS0/REF0 VSSR XIN XOUT VDDAGP *MODE/AGP0 *SELP4_K7#/AGP1 *PCI_STP# VSSAGP **FS1/PCI_F PCI1 *MULTSEL/PCI2 VSSPCI PCI3 PCI4 VDDPCI PCI5 *CPU_STP# VSS48M **FS3/48M **FS2/24_48M VDD48M VDD VSS IREF *PD# SCLK SDATA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VTTPWRGD#/REF1 VDDR VSSC CPUT/CPUOD_T CPUC/CPUOD_C VDDC VDDI CPUCS_C CPUCS_T VSSI FBOUT BUF_IN DDRT0 DDRC0 DDRT1 DDRC1 VDDD VSSD DDRT2 DDRC2 DDRT3 DDRC3 VDDD VSSD DDRT4 DDRC4 DDRT5 DDRC5
FS0
PCI_STP# CPU_STP# PD#
PLL1 FS2
CY28347
SDATA SCLK
SMBus
PLL2
/2
VDD48M 48M
24_48M
SELSDR_DDR# S2D CONVERT
VDDD FBOUT DDRT(0:5) DDRC(0:5)
BUF_IN
Note: 1. Pins marked with [*] have internal pull-up resistors. Pins marked with [**] have internal pull-down resistors.
Rev 1.0, November 20, 2006
2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550
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www.SpectraLinear.com
CY28347
Pin Description
Pin 3 4 1 XIN XOUT FS0/REF0 VDD VDD
[2]
Name
PWR
I/O I O
Description Oscillator Buffer Input. Connect to a crystal or to an external clock. Oscillator Buffer Output. Connect to a crystal. Do not connect when an external clock is applied at XIN.
I/O Power-on Bidirectional Input/Output. At power-up, FS0 is the input. When the PU power supply voltage crosses the input threshold voltage, FS0 state is latched and this pin becomes REF0, buffered copy of signal applied at XIN. (1-2 x strength, selectable by SMBus. Default value is 1 x strength.) I If SELP4_K7# = 1, with a P4 processor setup as CPU(T:C). At power-up, VTT_PWRGD# is an input. When this input is sampled LOW, the FS (3:0) and MULTSEL are latched and all output clocks are enabled. After the first transition to a LOW on VTT_PWRGD#, this pin is ignored and will not effect the behavior of the device thereafter. When the VTT_PWRGD# feature is not used, please connect this signal to ground through a 10K resistor. If SELP4_K7# = 0, with an Athlon (K7) processor as CPUOD_(T:C). VTT_PWRGD# function is disabled, and the feature is ignored. This pin becomes REF1 and is a buffered copy of the signal applied at XIN. These pins are configured for DDR clock outputs. They are "True" copies of signal applied at Pin45, BUF_IN. These pins are configured for DDR clock outputs. They are "Complementary" copies of signal applied at Pin45, BUF_IN.
56
VTTPWRGD#
VDDR
REF1
VDDR
O
44,42,38, DDRT(0:5) 36,32,30 43,41,37 35,31,29 7 DDRC(0:5) SELP4_K7#/ AGP1
VDDD VDDD
O O
VDDAGP I/O Power-on Bidirectional Input/Output. At power-up, SELP4_K7# is the input. PU When the power supply voltage crosses the input threshold voltage, SELP4_K7# state is latched and this pin becomes AGP1 clock output. SELP4_K7# = 1 selects P4 mode. SELP4_K7# = 0 selects K7 mode. I/O Power-on Bidirectional Input/Output. At power-up, MULTSEL is the input. When PU the power supply voltage crosses the input threshold voltage, MULTSEL state is latched and this pin becomes PCI2 clock output. MULTSEL = 0, Ioh is 4 x IREFMULTSEL = 1, Ioh is 6 x IREF O 3.3V True CPU Clock Outputs. This pin is programmable through strapping pin7, SELP4_K7#. If SELP4_K7# = 1, this pin is configured as the CPUT Clock Output. If SELP4_K7# = 0, this pin is configured as the CPUOD_T Open Drain Clock Output. See Table 1. 3.3V Complementary CPU Clock Outputs. This pin is programmable through strapping pin7, SELP4_K7#. If SELP4_K7# = 1, this pin is configured as the CPUC Clock Output. If SELP4_K7# = 0, this pin is configured as the CPUOD_C Open Drain Clock Output. See Table 1. PCI Clock Outputs. Are synchronous to CPU clocks. See Table 1. 2.5V CPU Clock Outputs for Chipset. See Table 1.
12
MULTSEL/PCI2 VDDPCI
53
CPUT/CPUOD_T
VDDC
52
CPUC/CPUOD_C
VDDC
O
14,15,17 48,49 18
PCI (3:5) CPUCS_T/C CPU_STP#
VDDPCI VDDI VDDPCI
O O
I If pin 6 is pulled down at power on reset, then this pin becomes CPU_STP#. When PU CPU_STP# is asserted LOW, then both of the CPU signals stop at the next HIGH to LOW transition or stays LOW if it already is LOW. This does not stop the CPUCS signals. I/O Power-on Bidirectional Input/Output. At power-up, FS1 is the input. When the PD power supply voltage crosses the input threshold voltage, FS1 state is latched and this pin becomes PCI_F clock output.
10
FS1/PCI_F
VDDPCI
20
FS3/48M
VDD48M I/O Power-on Bidirectional Input/Output. At power-up, FS3 is the input. When the PD power supply voltage crosses the input threshold voltage, FS3 state is latched and this pin becomes 48M, a USB clock output. VDDPCI O PCI Clock Output. VDD48M I/O Power-on Bidirectional Input/Output. At power-up, FS2 is the input. When the PD power supply voltage crosses the input threshold voltage, FS2 state is latched and this pin becomes 24_48M, a SIO programmable clock output.
(range 200 k to 500 k ).
11 21
PCI1 FS2/24_48M
Note: 2. PU = internal pull-up. PD = internal pull-down. Typically = 250 k
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CY28347
Pin Description (continued)[2]
Pin 6 Name MODE/AGP0 PWR I/O Description VDDAGP I/O Power-on Bidirectional Input/Output. At power-up, MODE is an input and PU becomes AGP0 output after the power supply voltage crosses the input threshold voltage. Must have 10K resistor to VSS. See Table 2. VDDAGP I If pin 6 is pulled down at power on reset, then this pin becomes PCI_STP#. PU When PCI_STP# is asserted LOW, then all of the PCI signals, except the PCI_F, stops at the next HIGH to LOW transition or stays LOW if it already is LOW. I Current reference programming input for CPU buffers. A precise resistor is attached to this pin, which is connected to the internal current reference.
8
PCI_STP#
25 28
IREF SDATA
I/O Serial Data Input. Conforms to the SMBus specification of a Slave Receive/Transmit device. It is an input when receiving data. It is an open drain output when acknowledging or transmitting data. I Serial Clock Input. Conforms to the SMBus specification. I When PD# is asserted LOW, the device enters power down mode. See power PU management function. I O 2.5V CMOS type input to the DDR differential buffers. This is the single-ended, SDRAM buffered output of the signal applied at BUF_IN. It is in phase with the DDRT(0:5) signals. 3.3V power supply for AGP clocks. 3.3V power supply for CPU (T: C) clocks. 3.3V power supply for PCI clocks. 3.3V power supply for REF clock. 2.5V power supply for CPUCS_T/C clocks. 3.3V power supply for 48M. 3.3V Common power supply. 2.5V power supply for DDR clocks. Ground for AGP clocks. Ground for PCI clocks. Ground for CPU (T:C) clocks. Ground for DDR clocks. Ground for 48M clock. Ground for CPUCS_T/C clocks. Common ground.
27 26 45 46 5 51 16 55 50 22 23 34,40 9 13 54 33,39 19 47 24
SCLK PD# BUF_IN FBOUT VDDAGP VDDC VDDPCI VDDR VDDI VDD48M VDD VDDD VSSAGP VSSPCI VSSC VSSD VSS48M VSSI VSS
Table 2. MODE Pin-Power Management Input Control MODE, Pin 6 (Latched Input) 0 Invalid Pin 26 PD# Reserved Board Target Trace/Term Z 50 Ohm 50 Ohm CPU_STP# Reserved Reference R, IREF = VDD/(3*Rr) Rr = 221 1%, IREF = 5.00 mA Rr = 475 1%, IREF = 2.32 mA Pin 18 PCI_STP# Reserved Pin 8
Table 3. Swing Select Functions Through Hardware MULTSEL 0 1 Output Current IOH = 4* Iref IOH = 6* Iref VOH@Z 1.0V@50 0.7V@50
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CY28347
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions such as individual clock output buffers, etc., can be individually enabled or disabled. The registers associated with the Serial Data Interface initializes to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface can also be used during system operation for power management functions. Table 4. Command Code Definition Bit 7 (6:0) 0 = Block Read or Block Write operation 1 = Byte Read or Byte Write operation Byte offset for Byte Read or Byte Write operation. For Block Read or Block Write operations, these bits should be "0000000" Description
Data Protocol
The clock driver serial protocol accepts Byte Write, Byte Read, Block Write, and Block Read operation from the controller. For Block Write/Read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For Byte Write and Byte Read operations, the system controller can access individual indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 4. The Block Write and Block Read protocol is outlined in Table 5 while Table 6 outlines the corresponding Byte Write and Byte Read protocol. The slave receiver address is 11010010 (D2H).
Table 5. Block Read and Block Write Protocol Block Write Protocol Bit 1 2:8 9 10 11:18 19 20:27 28 29:36 37 38:45 46 .... .... .... .... Description Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 Bit "00000000" stands for block operation Acknowledge from slave Byte Count - 8 bits Acknowledge from slave Data byte 0 - 8 bits Acknowledge from slave Data byte 1 - 8 bits Acknowledge from slave Data Byte N/Slave Acknowledge... Data Byte N - 8 bits Acknowledge from slave Stop Bit 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39:46 47 48:55 56 .... .... .... .... Table 6. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 2:8 9 Description Start Slave address - 7 bits Write Bit 1 2:8 9 Byte Read Protocol Description Start Slave address - 7 bits Write Block Read Protocol Description Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 Bit "00000000" stands for block operation Acknowledge from slave Repeat start Slave address - 7 bits Read Acknowledge from slave Byte count from slave - 8 bits Acknowledge Data byte from slave - 8 bits Acknowledge Data byte from slave - 8 bits Acknowledge Data bytes from slave/Acknowledge Data byte N from slave - 8 bits Not Acknowledge Stop
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CY28347
Table 6. Byte Read and Byte Write Protocol (continued) 10 11:18 Acknowledge from slave Command Code - 8 bits "1xxxxxxx" stands for byte operation bit[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Data Byte from Master - 8 Bits Acknowledge from slave Stop 10 11:18 Acknowledge from slave Command Code - 8 bits "1xxxxxxx" stands for byte operation bit[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Repeat start Slave address - 7 bits Read Acknowledge from slave Data byte from slave - 8 bits Not Acknowledge Stop
19 20:27 28 29
19 20 21:27 28 29 30:37 38 39
Byte 0: Frequency Select Register Bit 7 6 5 4 3 @Pup 0 H/W Setting H/W Setting H/W Setting 0 21 10 1 FS2 FS1 FS0 Pin# Name Reserved. For Selecting Frequencies see Table 1. For Selecting Frequencies see Table 1. For Selecting Frequencies see Table 1. If this bit is programmed to "1," it enables WRITES to bits (6:4,1) for selecting the frequency via software (SMBus) If this bit is programmed to a "0" it enables only READS of bits (6:4,1), which reflect the hardware setting of FS(0:3). 11 20 7 Reserved FS3 SELP4_K7# Reserved For Selecting frequencies in Table 1. Only for reading the hardware setting of the CPU interface mode, status of SELP4_K7# strapping. Description
2 1 0
H/W Setting H/W Setting H/W Setting
Byte 1: CPU Clocks Register Bit 7 6 5 4 3 2 1 @Pup 0 1 1 1 1 1 0 48,49 53,52 53,52 Pin# Name SSMODE SSCG SST1 SST0 CPUCS_T/C_ EN# CPUOD_T/C_EN# CPUT/C_PD_CNTRL Description 0 = Down Spread. 1 = Center Spread. See Table 10. 1 = Enable (default). 0 = Disable Select spread bandwidth. See Table 10. Select spread bandwidth. See Table 10. 1 = output enabled (running). 0 = output disabled asynchronously in a LOW state. 1 = output enabled (running). 0 = output disable asynchronously in a LOW state. In K7 mode, this bit is ignored. In P4 mode, when PD# asserted LOW, 0 = drive CPUT to 2xIref and CPUC LOW and 1 = three-state CPUT and CPUC. Only For reading the hardware setting of the Pin11 MULT0 value.
0
1
11
MULT0
Byte 2: PCI Clock Register Bit 7 6 5 @Pup 0 1 1 10 Pin# Name PCI_DRV PCI_F Description PCI clock output drive strength 0 = Normal, 1 = increase the drive strength 20%. 1 = output enabled (running). 0 = output disabled asynchronously in a LOW state. Reserved, set = 1.
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CY28347
Byte 2: PCI Clock Register (continued) Bit 4 3 2 1 0 @Pup 1 1 1 1 1 Pin# 17 15 14 12 11 Name PCI5 PCI4 PCI3 PCI2 PCI1 Description 1 = output enabled (running). 0 = output disabled asynchronously in a LOW state. 1 = output enabled (running). 0 = output disabled asynchronously in a LOW state. 1 = output enabled (running). 0 = output disabled asynchronously in a LOW state. 1 = output enabled (running). 0 = output disabled asynchronously in a LOW state. 1 = output enabled (running). 0 = output disabled asynchronously in a LOW state.
Byte 3: AGP/Peripheral Clocks Register Bit 7 6 5 4 3 2 1 0 @Pup 0 1 1 0 0 1 1 1 7 6 AGP1 AGP0 Pin# 21 20 21 6,7,8 6,7,8 Name 24_48M 48MHz 24_48M DASAG1 DASAG0 Description "0" = pin 21 output is 24 MHz. Writing a "1" into this register asynchronously changes the frequency at pin 21 to 48 MHz. 1 = output enabled (running). 0 = output disabled asynchronously in a LOW state. 1 = output enabled (running). 0 = output disabled asynchronously in a LOW state. Programming these bits allow shifting skew of the AGP(0:2) signals relative to their default value. See Table 7. Reserved, set = 1. 1 = output enabled (running). 0 = output disabled asynchronously in a LOW state. 1 = output enabled (running). 0 = output disabled asynchronously in a LOW state.
Byte 4: Peripheral Clocks Register Bit 7 6 5 4 3 2 1 0 @Pup 1 1 0 0 1 1 1 1 Pin# 20 21 6,7,8 6,7,8 1 56 1 56 Name 48M 24_48M DARAG1 DARAG0 REF0 REF1 REF0 REF1 Description 1 = strength x 1. 0= strength x 2 1 = strength x 1. 0= strength x 2 1 = strength x 1. 0= strength x 2 1 = strength x 1. 0= strength x 2 Programming these bits allow modifying the frequency ratio of the AGP(2:0), PCI(6:1, F) clocks relative to the CPU clocks. See Table 8. 1 = output enabled (running). 0 = output disabled asynchronously in a LOW state. 1 = output enabled (running). 0 = output disabled asynchronously in a LOW state. (K7 Mode only.) 1 = strength x 1. 0 = strength x 2 1 = strength x 1. 0 = strength x 2 (K7 Mode only)
Table 7. Dial-a-SkewTM AGP(0:2) DASAG (1:0) 00 01 10 11 AGP(0:2) Skew Shift Default -280 ps +280 ps +480 ps
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CY28347
Table 8. Dial-A-RatioTM AGP(0:2) DARAG (1:0) 00 01 10 11 Byte 5: DDR Clock Register Bit 7 6 5 4 3 2 1 0 @Pup 0 1 1 1 1 1 1 1 Pin# 45 46 29,30 31,32 35,36 37,38 41,42 43,44 Name FBOUT DDRT/C5 DDRT/C4 DDRT/C3 DDRT/C2 DDRT/C1 DDRT/C0 Description 1 = output enabled (running). 0 = output disabled asynchronously in a LOW state. 1 = output enabled (running). 0 = output disabled asynchronously in a LOW state. 1 = output enabled (running). 0 = output disabled asynchronously in a LOW state. 1 = output enabled (running). 0 = output disabled asynchronously in a LOW state. 1 = output enabled (running). 0 = output disabled asynchronously in a LOW state. 1 = output enabled (running). 0 = output disabled asynchronously in a LOW state. 1 = output enabled (running). 0 = output disabled asynchronously in a LOW state. BUF_IN threshold voltage DDR Mode, BUF_IN threshold setting. 0 = 1.15V, 1 = 1.05V. CU/AGP Ratio Frequency Selection Default 2/1 2.5/1 3/1
Byte 6: Reserve Register Bit 7 6 5 4 3 2 1 0 @Pup 1 0 0 0 0 0 0 0 Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Description
Byte 7: Dial-a-Frequency Control Register N Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Reserved N6, MSB N5 N4 N3 N2 N1 N0, LSB Name Description Reserved for device function test. These bits are for programming the PLL's internal N register. This access allows the user to modify the CPU frequency at very high resolution (accuracy). All other synchronous clocks (clocks that are generated from the same PLL, such as PCI) remain at their existing ratios relative to the CPU clock.
Rev 1.0, November 20, 2006
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CY28347
Byte 8: Silicon Signature Register (all bits are Read-only) Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 1 0 0 0 Name Revision_ID3 Revision_ID2 Revision_ID1 Revision_ID0 Vender_ID3 Vender_ID2 Vender_ID1 Vender_ID0 Revision ID bit [3] Revision ID bit [2] Revision ID bit [1] Revision ID bit [0] Cypress's Vendor ID bit [3] Cypress's VendorID bit [2] Cypress's Vendor ID bit [1] Cypress's Vendor ID bit [0] Description
Byte9: Dial-A-Frequency Control Register R Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 R5, MSB R4 R3 R2 R1 R0 DAF_ENB R and N register mux selection. 0=R and N values come from the ROM. 1=data is load from DAF (I2C) registers. Name Reserved These bits are for programming the PLL's internal R register. This access allows the user to modify the CPU frequency at very high resolution (accuracy). All other synchronous clocks (clocks that are generated from the same PLL, such as PCI) remain at their existing ratios relative to the CPU clock. Description
Dial-a-Frequency Feature
SMBus Dial-a-frequency feature is available in this device via Byte7 and Byte9. P is a PLL constant that depends on the frequency selection prior to accessing the Dial-a-Frequency feature. Table 9. FS(4:0) XXXXX P 96016000
Spread Spectrum Clock Generation (SSCG)
Spread Spectrum is enabled/disabled via SMBus register Byte 1, Bit 6. Table 10. Spread Spectrum Table Mode 0 0 0 0 1 1 1 1 SST1 0 0 1 1 0 0 1 1 SST0 0 1 0 1 0 1 0 1 % Spread -1.5% -1.0% -0.7% -0.5% 0.75% 0.5% 0.35% 0.25%
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CY28347
Maximum Ratings[3]
Input Voltage Relative to VSS:...............................VSS - 0.3V Input Voltage Relative to VDDQ or AVDD: ............. VDD + 0.3V Storage Temperature: ................................ -65 C to + 150 C Operating Temperature:.................................... 0 C to +70 C Maximum ESD............................................................. 2000V Maximum Power Supply: ................................................ 5.5V This device contains circuitry to protect the inputs against damage due to HIGH static voltages or electric field. However, precautions should be take to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, VIN and VOUT should be constrained to the range. VSS < (VIN or VOUT) < VDD Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD).
DC Parameters (VDD = VDDPCI = VDDAGP = VDDR = VDD48M = VDDC = 3.3V 5%, VDDI = VDD = 2.5 5%, TA = 0 C to +70 C)
Parameter VIL1 VIH1 VIL2 VIH2 Vol Iol Ioz Idd3.3V Idd2.5V Ipd Ipup Ipdwn Cin Cout Lpin Cxtal Description Input LOW Voltage Input HIGH Voltage Input LOW Voltage Input HIGH Voltage Output LOW Voltage for Sreset# Pull-down Current for Sreset# Three-state Leakage Current Dynamic Supply Current Dynamic Supply Current Power-down Supply current Internal Pull-up Device Current Internal Pull-down Device Current Input Pin Capacitance Output Pin Capacitance Pin Inductance Crystal Pin Capacitance Measured from the XIN or XOUT to VSS 27 36 CPU frequency set at PD# = 0 Input @ VSS Input @ VDD 133.3[4] 156 177 3.8 CPU frequency set at 133.3 MHz[4] IOL VOL = 0.4V Applicable to SDATA and SCLK 2.2 0.4 24 35 10 180 200 4.0 -25 10 5 6 7 45 Conditions Applicable to PD#, F S(0:4) 2.0 1.0 Min. Typ. Max. 1.0 Unit Vdc Vdc Vdc Vdc V mA A mA mA mA A A pF pF pF pF
AC Parameters
66 MHz Parameter Crystal TDC TPeriod VHIGH VLOW Tr / Tf TCCJ Txs Description Xin Duty Cycle Xin Period Xin HIGH Voltage Xin LOW Voltage Xin Rise and Fall Times Xin Cycle to Cycle Jitter Crystal Start-up Time Min. 45 69.84 0.7VDD 0 Max. 55 71.0 VDD 0.3VDD 10.0 500 30 100 MHz Min. 45 69.84 0.7VDD 0 Max. 55 71.0 VDD 0.3VDD 10.0 500 30 133 MHz Min. 45 69.84 0.7VDD 0 Max. 55 71.0 VDD 0.3VDD 10 500 30 200 MHz Min. 45 69.84 0.7VDD 0 Max. Unit 55 71.0 VDD 0.3VDD 10 500 30 Notes
% 5,6,7,8 ns 5,6,7,8 V 7,9 V ns 7 ps 10,11,12,13 ms 9
Notes: 3. Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 4. All outputs loaded as per maximum capacitative load table in P4 and DDR mode. See Table 12. 5. All outputs loaded as per loading specified in the loading table. See Table 12. 6. This measurement is applicable with Spread ON or spread OFF. 7. This is required for the duty cycle on the REF clock out to be as specified. The device will operate reliably with input duty cycles up to 30/70 but the REF clock duty cycle will not be within data sheet specifications. 8. The typical value of VX is expected to be 0.5*VDDD (or 0.5*VDDC for CPUCS signals) and will track the variations in the DC level of the same. 9. Measured between 0.2Vdd and 0.7Vdd. 10. Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V for 3.3V signals and between 0.4V and 2.0V for 2.5V signals, and between 20% and 80% for differential signals. 11. Probes are placed on the pins, and measurements are acquired at 2.4V for 3.3V signals and at 2.0V for 2.5V signals. 12. When Xin is driven from and external clock source (3.3V parameters apply). 13. When Crystal meets minimum 40 ohm device series resistance specification.
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CY28347
AC Parameters (continued)
66 MHz Parameter Description Min. 45 14.85 175 Max. 55 15.3 700 20% 125 100 150 280 45 14.85 175 430 55 15.3 467 125 100 150 510 760 325 510 280 45 9.85 175 P4 Mode CPU at 0.7V TDC CPUT/C Duty Cycle TPeriod Tr/Tf CPUT/C Period CPUT/C Rise and Fall Times Rise/Fall Matching Delta Tr/Tf Rise/Fall Time Variation TSKEW TCCJ Vcross CPUT/C to CPUCS_T/C Clock Skew CPUT/C Cycle-to-Cycle Jitter Crossing Point Voltage 100 MHz Min. 45 9.85 175 Max. 55 10.2 700 20% 125 100 150 430 55 10.2 467 125 100 150 760 325 510 280 45 7.35 175 133 MHz Min. 45 7.35 175 Max. 55 7.65 700 20% 125 100 150 430 55 7.65 467 125 100 150 760 325 510 280 45 4.85 175 200 MHz Min. 45 4.85 175 Max. Unit 55 5.1 700 20% 125 100 150 430 55 5.1 467 125 100 150 760 325 Notes
% 5,6,10,14,15 ns 5,6,10,14,15 ps 15,16 16,17 ps 10,15,16,18 ps 10,11,12,14,1 5 ps 6,10,11,12,14, 15 mV 15. % 5,10,6,14 nS 5,10,6,14 ps 10,11,19 ps 10,18 ps 10,11,12,14 ps 10,11,12,14 mV 19 ps 20
P4 Mode CPU at 1.0V TDC CPUT/C Duty Cycle TPeriod CPUT/C Period DifferCPUT/C Rise and Fall ential Tr/Tf Times Delta Tr/Tf Rise/Fall Time Variation TSKEW TCCJ Vcross CPUT/C to CPUCS_T/C Clock Skew CPUT/C Cycle-to-Cycle Jitter Crossing Point Voltage
SEAbsolute Single-ended DeltaSlew Rise/Fall Waveform Symmetry K7 Mode TDC CPUOD_T/C Duty Cycle TPeriod TLOW Tf TCCJ VD VX Chipset TDC CPUOD_T/C Period CPUOD_T/C LOW Time CPUOD_T/C Fall Time CPUOD_T/C Cycle-to-Cycle Jitter Differential Voltage AC Differential Crossover Voltage CPUCS_T/C Duty Cycle .4 500 45 14.85 2.8 0.4
55 15.3 1.6 250 Vp+.6V 1100
45 9.85 2.8 0.4
55 10.2 1.6 250
45 7.35 1.67 0.4
55 7.65 1.6 250
45 4.85 2.8 0.4
55 5.1 1.6 250
% 5,6,10 ns 5,6,10 ns 5,6,10 ns 5,10,21 ps 6,10 V 22 mV 23
.4 500
Vp+.6V 1100
.4 500
Vp+.6V 1100
.4 500
Vp+.6V 1100
45
55
45
55
45
55
45
55
% 5,10,6
Notes: 14. Measured at VX between the rising edge and the following falling edge of the signal. 15. Determined as a fraction of 2*(Trise-Tfall)/(Trise+Tfall). 16. See figure 6 for 0.7V loading specification. 17. Measurement taken from differential waveform, from -0.35V to +0.35V. 18. The time specified is measured from when all VDD's reach their respective supply rail (3.3V and 2.5V) till the frequency output is stable and operating within specifications. 19. Ideally the probes should be placed on the pins. If there is a transmission line between the test point and the pin for one signal of the pair (e.g., CPU), you should add the same length transmission line to the other signal of the pair (e.g., AGP). 20. Measured in absolute voltage, i.e., single-ended measurement. 21. Probes are placed on the pins, and measurements are acquired at 1.5V for 3.3V signals and at 1.25V for 2.5V, and 50% point for differential signals. 22. Measured at VX, or where subtraction of CLK-CLK# crosses 0 volts. 23. VD is the magnitude of the difference between the measured voltage level on a DDRT (and CPUCS_T) clock and the measured voltage level on its complementary DDRC (and CPUCS_C) one.
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AC Parameters (continued)
66 MHz Parameter TPeriod Tr / Tf VD VX AGP TDC TPeriod THIGH TLOW Tr/Tf TSKEW TCCJ PCI TDC TPeriod THIGH TLOW Tr/Tf TSKEW TCCJ 48 MHz TDC TPeriod Tr/Tf TCCJ 24 MHz TDC TPeriod Tr / Tf TCCJ Description CPUCS_T/C Period CPUCS_T/C Rise and Fall Times Differential Voltage AC Differential Crossover Voltage AGP(0:2) Duty Cycle AGP(0:2) Period AGP(0:2) HIGH Time AGP(0:2) LOW Time AGP(0:2) Rise and Fall Times Any AGP to Any AGP Clock Skew AGP(0:2) Cycle-to-Cycle Jitter PCI(_F,1:6) Duty Cycle PCI(_F,1:6) Period PCI(_F,1:6) HIGH Time PCI(_F,1:6) LOW Time PCI(_F,1:6) Rise and Fall Times Any PCI to Any PCI Clock Skew PCI(_F,1:6) Cycle-to-Cycle Jitter 48-MHz Duty Cycle 48-MHz Period 48-MHz Rise and Fall Times 48-MHz Cycle-to-Cycle Jitter 24-MHz Duty Cycle 24-MHz Period 24-MHz Rise and Fall Times 24-MHz Cycle-to-Cycle Jitter 45 1.0 45 1.0 45 30.0 12.0 12.0 0.5 2.0 500 500 Min. 15 0.4 0.4 Max. 15.5 1.6 Vp+ 0.6V 100 MHz Min. 10.0 0.4 0.4 Max. 10.5 1.6 Vp+ 0.6V 133 MHz Min. 7.35 0.4 0.4 Max. 7.65 1.6 Vp+ 0.6V 200 MHz Min. 4.85 0.4 0.4 Max. Unit 5.1 1.6 Vp+ 0.6V Notes ns 5,10,6 ns 5,10,21 V 24 V 14
0.5*VD 0.5*VD 0.5*VD 0.5*VD 0.5*VD 0.5*VD 0.5*VD 0.5*VD DI-0.2 DI+0.2 DI-0.2 DI+0.2 DI-0.2 DI+0.2 DI-0.2 DI+0.2 45 15 5.25 5.05 0.4 1.6 250 500 55 16 45 15 5.25 5.05 0.4 1.6 250 500 55 16 45 15 5.25 5.05 0.4 1.6 250 500 55 16 45 15 5.25 5.05 0.4 1.6 250 500 55 16
% 5,6,10 ns 5,6,10 ns 10,25 ns 10,18 ns 10,21 ps 10,11,12 ps 6,10,11,12
55
45 30.0 12.0 12.0 0.5
55
45 30.0 12.0 12.0
55
45 30.0 12.0 12.0
55
% 5,6,10 ns 5,6,10 ns 10,25 ns 10,18
2.0 500 500
0.5
2.0 500 500
0.5
2.0 500 500
ns 10,21 ps 10,11,12 ps 10,6,11,12
55 4.0 500
45 1.0
55 4.0 500
45 1.0
55 4.0 500
45 1.0
55 4.0 500
% 5,6,10 ns 10,21 ps 10,6,11,12
20.8299 20.8333 20.8299 20.8333 20.8299 20.8333 20.8299 20.8333 ns 5,6,10
55 4.0 500
45 1.0
55 4.0 500
45 1.0
55 4.0 500
45 1.0
55 4.0 500
% 5,6,10 ns 10,21 ps 6,10,11,12
41.660 41.667 41.660 41.667 41.660 41.667 41.660 41.667 ns 5,6,10
Notes: 24. Measured at VX between the falling edge and the following rising edge of the signal. 25. Probes are placed on the pins, and measurements are acquired at 0.4V.
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AC Parameters (continued)
66 MHz Parameter REF TDC TPeriod Tr/Tf TCCJ DDR VX VD TDC TPeriod Tr/Tf TSKEW TCCJ THPJ TDelay TSKEW tstable Description REF Duty Cycle REF Period REF Rise and Fall Times REF Cycle-to-Cycle Jitter Min. 45 69.8413 1.0 Max. 55 71.0 4.0 1000 100 MHz Min. 45 69.8413 1.0 Max. 55 71.0 4.0 1000 133 MHz Min. 45 69.8413 1.0 Max. 55 71.0 4.0 1000 200 MHz Min. 45 69.8413 1.0 Max. Unit 55 71.0 4.0 1000 Notes
% 5,10,6 ns 5,6,10 ns 10,21 ps 6,10,11,12
Crossing Point Voltage of 0.5*VD 0.5*VD 0.5*VD 0.5*VD 0.5*VD 0.5*VD 0.5*VD 0.5*VD V 23 DDRT/C DD-0.2 DD+0.2 DD-0.2 DD+0.2 DD-0.2 DD+0.2 DD-0.2 DD+0.2 Differential Voltage Swing DDRT/C(0:5) Duty Cycle DDRT/C(0:5) Period DDRT/C(0:5) Rise/Fall Slew Rate DDRT/C to Any DDRT/C Clock Skew DDRT/C(0:5) Cycle-to-Cycle Jitter DDRT/C(0:5) Half Period Jitter BUF_IN to Any DDRT/C Delay FBOUT to Any DDRT/C Skew All Clock Stabilization from Power-up 1 0.7 45 14.85 1 VDDD + 0.6 55 15.3 3 100 75 100 4 100 1.5 1 0.7 45 9.85 1 VDDD + 0.6 55 10.2 3 100 75 100 4 100 1.5 1 0.7 45 14.85 1 VDDD + 0.6 55 15.3 3 100 75 100 4 100 1.5 1 0.7 45 9.85 1 VDDD + V 22 0.6 55 10.2 3 100 75 100 4 100 1.5 % 14 ns 14 V/ns 21 ps 10,11,14 ps 10,11,14 ps 10,11,14 ns 6,10 ps 6,10 ms 12
Connection Circuit DDRT/C Signals
TPCB DDRT
Measurement Point
16 pF 100
DDRC
TPCB
Measurement Point
16 pF
Figure 1. Differential DDR Termination
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For Open Drain CPU Output Signals (with K7 Processor SELP4_K7# = 0)
3.3V 60.4 Ohm CPUOD_T 47 Ohm 52 Ohm 5" 680 pF 500 Ohm 301 Ohm 47 Ohm CPUOD_C 52 Ohm 5" 680 pF 60.4 Ohm 500 Ohm 3.3V 20 pF VDDCPU(1.5V) 52 Ohm 1" 500 Ohm 52 Ohm " 20 pF VDDCPU(1.5V) 500 Ohm
Measurement Point
Measurement Point
Figure 2. K7 Termination
6"
6"
Figure 3. Chipset Termination For Differential CPU Output Signals (with P4 Processor SELP4_K7#= 1)
The following diagram shows lumped test load configurations for the differential Host Clock Outputs. Figure 4 is for the 1.0V
amplitude signalling and Figure 5 is for the 0.7V amplitude signalling.
33.2 2 pF
TPCB CPUT
Measurement Point
MULTSEL CPUC IREF
221
475
TPCB
63.4
33.2 2 pF
Measurement Point
63.4
Figure 4. P4 1.0V Configuration
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T PCB
49.9 2 pF
33
CPUT
Measurem ent Point
MULTSEL
33
T PCB
49.9 2 pF
Measurem ent Point
CPUC IREF
475
Figure 5. P4 0.7V Configuration Table 11.Group Timing Relationships and Tolerances Offset (ps) Tolerance (ps) Conditions
tCSAGP tAP
Table 12.Signal Loading
CPUCS to AGP AGP to PCI
750 500
500 500
CPUCS Leads AGP Leads
Clock Name
Max. Load (in pF)
REF (0:1), 48MHz (USB), 24_48MHz AGP(0:2), PCI_F(0:5)SDRAM (0:11) FBOUT DDRT/C CPUT/C CPUOD_T/C CPUCS_T/C
20 30 10 See Figure 1 See Figure 4 and Figure 5 See Figure 2 See Figure 3
0 ns
10 ns
20 ns
30 ns
CPU CLOCK 66.6 MHz CPU CLOCK 100 MHz CPU CLOCK 133.3 MHz tCSAGP AGP CLOCK 66.6 MHz tAP PCI CLOCK 33.3 MHz
Figure 6. Clock Timing Relationships
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CPU_STP# Assertion (P4 Mode)
When CPU_STP# pin is asserted, all CPU outputs will be stopped after being sampled by two rising CPUC clock edges. The final state of the stopped CPU signal is CPUT = HIGH and CPUC = LOW. There is no change to the output drive current values during the stopped state. The CPUT is driven HIGH with a current value equal to (Mult 0 "select") x (Iref), and the CPUC signal will not be driven. Due to external pulldown circuitry CPUC will be LOW during this stopped state.
CPU_STP# CPUT CPUC
Figure 7. CPU_STP# Assertion Waveform (P4 Mode) Table 13.CPU_STP# Functionality CPU_STP# CPU#4 CPU
CPU_STP# Deassertion (P4 Mode)
Normal Float The deassertion of the CPU_STP# signal will cause all CPU outputs that were stopped to resume normal operation in a synchronous manner. Synchronous manner meaning that no short or stretched clock pulses will be produce when the clock resumes. The maximum latency from the deassertion to active outputs is no more than two CPU clock cycles.
1 0
Normal Iref*Mult
CPU_STP# CPUT CPUC CPUCS_T CPUCS_C
Figure 8. CPU_STP# Deassertion Waveform (P4 Mode)
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CY28347
CPU_STP# Assertion (K7 Mode)
When CPU_STP# pin is asserted, all CPU outputs will be stopped after being sampled by two rising CPUC clock edges. The final state of the stopped CPU signal is CPUOD_T = LOW and CPUOD_C = LOW.
CPU_STP# CPUOD_T CPUOD_C
Figure 9. CPU_STP# Assertion Waveform (K7 Mode)
CPU_STP# Deassertion (K7 Mode)
The deassertion of the CPU_STP# signal will cause all CPU outputs that were stopped to resume normal operation in a synchronous manner. Synchronous manner meaning that no short or stretched clock pulses will be produce when the clock resumes. The maximum latency from the deassertion to active outputs is no more than two CPU clock cycles.
CPU_STP# CPUOD_T CPUOD_C CPUCS_T CPUCS_C
Figure 10. CPU_STP# Deassertion Waveform (K7 Mode)
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CY28347
PCI_STP# Assertion
The PCI_STP# signal is an active LOW input used for synchronous stopping and starting the PCI outputs while the rest of the clock generator continues to function. The setup time for capturing PCI_STP# going LOW is 10 ns (tsetup). The PCI_F clock will not be affected by this pin.
t setup
PCI_STP# PCI_F PCI(1:6)
Figure 11. PCI_STP# Assertion Waveform
PCI_STP#- Deassertion
The deassertion of the PCI_STP# signal will cause all PCI clocks to resume running in a synchronous manner within one PCI clock period after PCI_STP# transitions to a HIGH level.
t setup
PCI_STP# PCI_F PCI(1:6)
Figure 12. PCI_STP# Deassertion Waveform
Power Management Functions
All clocks can be individually enabled or stopped via the 2-wire control interface. All clocks maintain valid HIGH period on transitions from running to stop and on transitions from stopped to running when the chip was not powered OFF.
Power Down Assertion (P4 Mode)
When PD# is sampled LOW by two consecutive rising edges of CPUC clock then all clocks must be held LOW on their next HIGH to LOW transition. CPUT clocks must be held with a value of 2 x Iref,
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CY28347
P4 Processor SELP4_K7# = 1.
PW RDW N# CPUT 133MHz CPUC 133MHz PCI 33MHz AGP 66MHz USB 48MHz REF 14.318MHz DDRT 133MHz DDRC 133MHz
Figure 13. Power-down Assertion Timing Waveform (in P4 Mode)
Power-down Deassertion (P4 Mode)
The power-up latency needs to less than 1.5mS.
<1.5 m sec PW R D W N # C P U T 133M H z C P U C 133M H z PC I 33M H z AG P 66M H z U SB 48M H z R EF 14.318M H z D D R T 133M H z D D R C 133M H z
Figure 14. Power-down Deassertion Timing Waveform (in P4 Mode)
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AMD K7 processor SELP4_K7# = 0 Power-down Assertion (K7 Mode)
When the PD# signal is asserted LOW, all clocks are disabled to a LOW level in an orderly fashion prior to removing power from the CPU. When PD# is sampled LOW by two consecutive rising edges of the CPUCS_C clock, then all affected clocks are stopped in a LOW state after the next HIGH to LOW
PW RDW N# CPUOD_T 133MHz CPUCS_T 133MHz CPUOD_C 133MHz CPUCS_C 133MHz PCI 33MHz AGP 66MHz USB 48MHz REF 14.318MHz DDRT 133MHz DDRC 133MHz
transition or remains LOW. When in power-down (and before power is removed), all outputs are synchronously stopped in a LOW state (see Figure 15 below), all PLLs are shut off, and the crystal oscillator is disabled. When the device is shutdown, the I2C function is also disabled.
Figure 15. Power-down Assertion Timing Waveform (in K7 Mode)
Power Down Deassertion (K7 Mode)
When deasserted PD# to HIGH level, all clocks are enabled and start running on the rising edge of the next full period in
<1.5 msec PW RDW N# CPUOD_T 133MHz CPUCS_T 133MHz CPUOD_C 133MHz CPUCS_C 133MHz PCI 33MHz AGP 66MHz USB 48MHz REF 14.318MHz DDRT 133MHz DDRC 133MHz
order to guarantee a glitch-free operation, no partial clock pulses.
Figure 16. Power-down Deassertion Timing Waveform (in K7 Mode)
Rev 1.0, November 20, 2006
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CY28347
VID (0:3), SEL (0,1) VTT_PWRGD# PWRGD
VDD Clock Gen Clock State State 0
0.2-0.3mS Delay State 1
Wait for VTT_GD#
Sample Sels State 2 State 3 (Note A)
Clock Outputs
Off
On
Clock VCO
Off
On
Figure 17. VTT_PWGD# Timing Diagram (With Advanced PIII Processor SELP4_K7# = 1)[26]
W RG D# ow =L
S1
TP
S2
D e la y 0 .2 5 m S
S a m p le In p u ts F S ( 3 :0 )
W a it f o r 1 .1 4 6 m s
VT
E n a b le O u tp u te s
V D D A = 2 .0 V
S0
S3
P o w e r O ff
V D D 3 .3 = O ff
N o rm a l O p e r a tio n
Figure 18. Clock Generator Power-up/Run State Diagram (with P4 Processor SELP4_K7# = 1)
Ordering Information
Part Number Package Type Product Flow
CY28347OC CY28347OCT CY28347ZC CY28347ZCT
56-pin Shrunk Small Outline Package (SSOP) 56-pin Shrunk Small Outline Package (SSOP) - Tape and Reel 56-pin Thin Shrunk Small Outline package (TSSOP) 56-pin Thin Shrunk Small Outline package (TSSOP) - Tape and Reel
Commercial, 0 to 70 C Commercial, 0 to 70 C Commercial, 0 to 70 C Commercial, 0 to 70 C
Note: 26. This timing diagram shows that VTT_PWRGD# transits to a logic LOW in the first time at power up. After the first HIGH to LOW transition of VTT_PWRGD#, device is not affected, VTT_PWRGD# is ignored.
Rev 1.0, November 20, 2006
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CY28347
Package Drawing and Dimensions
56-lead Shrunk Small Outline Package O56
51 85062 *C
56-Lead Thin Shrunk Small Outline Package, Type II (6 mm x 14 mm) Z56
While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice.
Rev 1.0, November 20, 2006
Page 21 of 21

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